Embedded Systems: Hardware, Design and Implementation

4

Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors

TAREQ HASAN KHAN and KHAN WAHID

4.1 INTRODUCTION

Commercial high-speed image sensors [1–6] send pixels in a raster-scan fashion, and at a much higher rate compared with the speed of conventional low-cost microcontroller units (MCUs), such as Alf and Vegard’s Risc (AVR) [7], Peripheral Interface Controller (PIC) [8], and so on. As a result, random access of image pixels and their real-time processing is not possible. Besides, inside the image sensors, no buffering is provided. Hence, given the limited size of internal memory in these microcontrollers, storing a complete high-resolution image frame and accessing pixels randomly of the same frame are also an issue. We have recently offered a low-cost solution to the abovementioned problems by introducing a bridge hardware, referred to as iBRIDGE, that bridges the speed gap between high-speed image sensors and low-speed microcontrollers (or image processors) [9]. The iBRIDGE offers several features such as random access of image pixels for any digital video port (DVP)-based image sensors, memory buffering, on-chip clock generator, built-in inter-integrated circuit (I2C) protocol [10], power management, and so on.

However, the first iBRIDGE design suffers from a few shortcomings, such as the large number of inputs/outputs (I/Os); as a result, the microcontroller also needs a large number of I/Os for interfacing. Although the first iBRIDGE allows ...