FPGA-Based Emulation Support for Design Space Exploration



Simulation has always been at the heart of design space exploration (DSE). Every decision that is taken during the exploration of different design alternatives has to be supported by some sort of simulation tool. The accuracy provided by this evaluation tool has a significant impact on the overall quality of the exploration process, reducing the uncertainty of the design choices. At the same time, DSE processes often require numerous architecture evaluations to be performed in order to converge at least to a suboptimal maximization of some performance function. Therefore, the time required for each architecture evaluation step has to be minimized to be able to repeat a high number of evaluation steps as required by the exploration algorithm. These two contrasting needs define a trade-off between simulation accuracy and simulation speed that constrains the choice of which simulation infrastructure to use to support the DSE.

Today, the majority of architectural simulation is still performed at maximum accuracy (i.e., cycle level) in software. Among the most famous simulators, many are still sequential, like SimpleScalar [1], Simics [2], Gem5 [3], or MPArm [4]. In order to respond to the increasing system complexity, both in terms of the number of processing units (multicore design) and component heterogeneity (accelerators, application-specific architectures), ...

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