Embedded Systems: Hardware, Design and Implementation

10

Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip

SUDEEP PASRICHA and YONG ZOU

10.1 INTRODUCTION

Advances in complementary metal–oxide–semiconductor (CMOS) fabrication technology in recent years have led to the emergence of chip multiprocessors (CMPs) as compact and powerful computing paradigms. However, to keep up with rising application complexity, it is widely acknowledged that solutions beyond aggressive CMOS scaling into deeper nanometer technologies will be required in the near future, to improve CMP computational capabilities [1]. Three-dimensional integrated circuit (3D-IC) technology with wafer-to-wafer bonding [2, 3] has been recently proposed as a promising candidate for future CMPs. In contrast to traditional two-dimensional integrated circuit (2D-IC)-based chips that have a single layer of active devices (processors, memories), wafer-to-wafer bonded 3D-ICs consist of multiple stacked active layers and vertical through-silicon vias (TSVs) to connect the devices across the layers. Multiple active layers in 3D-ICs can enable increased integration of cores within the same area footprint as traditional 2D-ICs. In addition, long global interconnects between cores can be replaced by shorter interlayer TSVs, improving performance and reducing on-chip power dissipation. Recent 3D-IC test chips from IBM [2], Tezzaron [3], and Intel [4] have confirmed the benefits of 3D-IC technology.

A major challenge facing the design of such highly integrated 3D-ICs ...