Energy-Aware Memory Management for Embedded Multimedia Systems

Table of contents

1. Front Cover
2. Contents
3. Contributors
4. 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (1/4)
5. 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (2/4)
6. 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (3/4)
7. 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (4/4)
8. 2. The Power of Polyhedra (1/10)
9. 2. The Power of Polyhedra (2/10)
10. 2. The Power of Polyhedra (3/10)
11. 2. The Power of Polyhedra (4/10)
12. 2. The Power of Polyhedra (5/10)
13. 2. The Power of Polyhedra (6/10)
14. 2. The Power of Polyhedra (7/10)
15. 2. The Power of Polyhedra (8/10)
16. 2. The Power of Polyhedra (9/10)
17. 2. The Power of Polyhedra (10/10)
18. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (1/10)
19. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (2/10)
20. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (3/10)
21. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (4/10)
22. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (5/10)
23. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (6/10)
24. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (7/10)
25. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (8/10)
26. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (9/10)
27. 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (10/10)
28. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (1/7)
29. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (2/7)
30. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (3/7)
31. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (4/7)
32. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (5/7)
33. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (6/7)
34. 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (7/7)
35. 5. Storage Allocation for Streaming-Based Register File (1/9)
36. 5. Storage Allocation for Streaming-Based Register File (2/9)
37. 5. Storage Allocation for Streaming-Based Register File (3/9)
38. 5. Storage Allocation for Streaming-Based Register File (4/9)
39. 5. Storage Allocation for Streaming-Based Register File (5/9)
40. 5. Storage Allocation for Streaming-Based Register File (6/9)
41. 5. Storage Allocation for Streaming-Based Register File (7/9)
42. 5. Storage Allocation for Streaming-Based Register File (8/9)
43. 5. Storage Allocation for Streaming-Based Register File (9/9)
44. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (1/9)
45. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (2/9)
46. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (3/9)
47. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (4/9)
48. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (5/9)
49. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (6/9)
50. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (7/9)
51. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (8/9)
52. 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (9/9)
53. 7. Leakage Current Mechanisms and Estimation in Memories and Logic (1/4)
54. 7. Leakage Current Mechanisms and Estimation in Memories and Logic (2/4)
55. 7. Leakage Current Mechanisms and Estimation in Memories and Logic (3/4)
56. 7. Leakage Current Mechanisms and Estimation in Memories and Logic (4/4)
57. 8. Leakage Control in SoCs (1/5)
58. 8. Leakage Control in SoCs (2/5)
59. 8. Leakage Control in SoCs (3/5)
60. 8. Leakage Control in SoCs (4/5)
61. 8. Leakage Control in SoCs (5/5)
62. 9. Energy-Efficient Memory Port Assignment (1/6)
63. 9. Energy-Efficient Memory Port Assignment (2/6)
64. 9. Energy-Efficient Memory Port Assignment (3/6)
65. 9. Energy-Efficient Memory Port Assignment (4/6)
66. 9. Energy-Efficient Memory Port Assignment (5/6)
67. 9. Energy-Efficient Memory Port Assignment (6/6)
68. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (1/7)
69. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (2/7)
70. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (3/7)
71. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (4/7)
72. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (5/7)
73. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (6/7)
74. 10. Energy-Efficient Address-Generation Units and Their Design Methodology (7/7)