Book description
Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach presents recent computer-aided design (CAD) ideas that address memory management tasks, particularly the optimization of energy consumption in the memory subsystem. It explains how to efficiently implement CAD solutions, including theoretical methods an
Table of contents
- Front Cover
- Contents
- Contributors
- 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (1/4)
- 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (2/4)
- 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (3/4)
- 1. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems (4/4)
- 2. The Power of Polyhedra (1/10)
- 2. The Power of Polyhedra (2/10)
- 2. The Power of Polyhedra (3/10)
- 2. The Power of Polyhedra (4/10)
- 2. The Power of Polyhedra (5/10)
- 2. The Power of Polyhedra (6/10)
- 2. The Power of Polyhedra (7/10)
- 2. The Power of Polyhedra (8/10)
- 2. The Power of Polyhedra (9/10)
- 2. The Power of Polyhedra (10/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (1/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (2/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (3/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (4/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (5/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (6/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (7/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (8/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (9/10)
- 3. Computation of Data Storage Requirements for Affine Algorithmic Specifications (10/10)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (1/7)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (2/7)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (3/7)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (4/7)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (5/7)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (6/7)
- 4. Polyhedral Techniques for Parametric Memory Requirement Estimation (7/7)
- 5. Storage Allocation for Streaming-Based Register File (1/9)
- 5. Storage Allocation for Streaming-Based Register File (2/9)
- 5. Storage Allocation for Streaming-Based Register File (3/9)
- 5. Storage Allocation for Streaming-Based Register File (4/9)
- 5. Storage Allocation for Streaming-Based Register File (5/9)
- 5. Storage Allocation for Streaming-Based Register File (6/9)
- 5. Storage Allocation for Streaming-Based Register File (7/9)
- 5. Storage Allocation for Streaming-Based Register File (8/9)
- 5. Storage Allocation for Streaming-Based Register File (9/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (1/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (2/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (3/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (4/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (5/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (6/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (7/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (8/9)
- 6. Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations (9/9)
- 7. Leakage Current Mechanisms and Estimation in Memories and Logic (1/4)
- 7. Leakage Current Mechanisms and Estimation in Memories and Logic (2/4)
- 7. Leakage Current Mechanisms and Estimation in Memories and Logic (3/4)
- 7. Leakage Current Mechanisms and Estimation in Memories and Logic (4/4)
- 8. Leakage Control in SoCs (1/5)
- 8. Leakage Control in SoCs (2/5)
- 8. Leakage Control in SoCs (3/5)
- 8. Leakage Control in SoCs (4/5)
- 8. Leakage Control in SoCs (5/5)
- 9. Energy-Efficient Memory Port Assignment (1/6)
- 9. Energy-Efficient Memory Port Assignment (2/6)
- 9. Energy-Efficient Memory Port Assignment (3/6)
- 9. Energy-Efficient Memory Port Assignment (4/6)
- 9. Energy-Efficient Memory Port Assignment (5/6)
- 9. Energy-Efficient Memory Port Assignment (6/6)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (1/7)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (2/7)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (3/7)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (4/7)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (5/7)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (6/7)
- 10. Energy-Efficient Address-Generation Units and Their Design Methodology (7/7)
Product information
- Title: Energy-Aware Memory Management for Embedded Multimedia Systems
- Author(s):
- Release date: November 2011
- Publisher(s): Chapman and Hall/CRC
- ISBN: 9781439814017
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