APPENDIX I
MINIMUM LIBRARY SYNTHESIS VERSUS FULL-LIBRARY SYNTHESIS OF A FOUR-BIT FLASH ADDER
To show the value of a richer stdcell library offering, I have attached these two netlists plus the equations from the original RTL. The following are two synthesized versions of a four-bit full adder. The first was synthesized using a minimum library: one FLIP-FLOP, one NAND2, one NOR2, and one INV. The second was synthesized using a fuller and richer library that is representative of those in the stdcell chapter of this book, complete with multiple drive strengths. It would be more beneficial to the reader to attempt to write up a register-transfer language (RTL) and synthesize it as opposed to copying these resulting netlists.
A general review will highlight that the richer library results are dramatically smaller and contain far fewer inversions (can run much faster). In addition, the reduction in the number of cells indicates the reduction in power consumption as well. The richer the stdcell library offering, the better the smaller, faster and less power hungry will be the designs synthesized with said library.
Note that the original RTL from which these came was rather stylized in that it defined the P and G signals and forced a true flash-add design. In that way, no full-adder or half-adder blocks were used. As noted in the stdcell chapter of the book, full-adder and half-adder blocks can be “abused” by the algorithms in current synthesis tools. Without the forcing of a true flash-add ...
