Chapter 4
Architecture and Hardware Requirements
This chapter gives a comprehensive overview of architecture and hardware requirements of turbo and LDPC decoders. It is written by the members of the Microelectronic Systems Design Research Group, University of Kaiserslautern, Germany. The main contributors are Timo Vogt, Torben Brack and Frank Kienle. The implementation issues of turbo decoders are described first, followed by LDPC decoder implementation issues.
4.1 Turbo Decoder Implementation
Previous chapters have presented turbo codes from a communications engineering point of view. Moving towards implementation, the architectural side of the decoder must be taken into account. This chapter gives an introduction to decoder architectures for parallel turbo codes followed by the implementation issues of the component decoders. For a comprehensive overview on turbo decoder architectures refer to [W01] [TGV+\02] [M02] [T05].
In the following, the discussion is restricted to the turbo and component decoder level. First we focus on interleaving and deinterleaving. The next two sections deal with serial component decoders that produce not more than one soft output in each cycle. After that, issues concerning parallel component decoder architectures are discussed.
4.1.1 Interleaver and Deinterleaver
The interleaver of a turbo encoder specifies a permutation of the original information ...
