book

ESD: Design and Synthesis

Name: ESD: Design and Synthesis
Author: Steven H. Voldman
ISBN: 9780470685716

by Steven H. Voldman

April 2011

Intermediate to advanced

290 pages

8h 7m

English

Wiley

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Cover
ESD Series By Steven H. Voldman
Title Page
Copyright
Dedication
About the Author
Preface
Acknowledgments
Chapter 1: ESD Design Synthesis
1.1 ESD Design Synthesis and Architecture Flow1.2 ESD Design – The Signal Path and the Alternate Current Path1.3 ESD Electrical Circuit and Schematic Architecture Concepts1.4 Mapping Semiconductor Chips and ESD Designs1.5 ESD Chip Architecture, and ESD Test Standards1.6 ESD Testing1.7 ESD Chip Architecture and ESD Alternative Current Paths1.8 ESD Networks, Sequencing, and Chip Architecture1.9 ESD Design Synthesis – Latchup-Free ESD Networks1.10 ESD Design Concepts – Buffering – Inter-Device1.11 ESD Design Concepts – Ballasting – Inter-Device1.12 ESD Design Concepts – Ballasting – Intra-Device1.13 ESD Design Concepts – Distributed Load Techniques1.14 ESD Design Concepts – Dummy Circuits1.15 ESD Design Concepts – Power Supply De-Coupling1.16 ESD Design Concepts – Feedback Loop De-Coupling1.17 ESD Layout and Floorplan-Related Concepts1.18 ESD Design Concepts – Analog Circuit Techniques1.19 ESD Design Concepts – Wire Bonds1.20 Design Rules1.21 Summary and Closing CommentsReferences
Chapter 2: ESD Architecture and Floorplanning
2.1 ESD Design Floorplan2.2 Peripheral I/O Design2.3 Lumped ESD Power Clamp in Peripheral I/O Design Architecture2.4 Lumped ESD Power Clamp in Peripheral I/O Design Architecture – Master/Slave ESD Power Clamp System2.5 Array I/O2.6 ESD Architecture – Dummy Bus Architectures2.7 Native Voltage Power Supply Architecture2.8 Mixed-Voltage Architecture2.9 Mixed-Signal Architecture2.10 Mixed-System Architecture – Digital and Analog CMOS2.11 Mixed-Signal Architecture – Digital, Analog, and RF Architecture2.12 Summary and Closing CommentsReferences

Chapter 3: ESD Power Grid Design
3.1 ESD Power Grid3.2 Semiconductor Chip Impedance3.3 Interconnect Failure and Dynamic on-Resistance3.4 Interconnect Wire and Via Guidelines3.5 ESD Power Grid Resistance3.6 Power Grid Layout Design3.7 ESD Specification Power Grid Considerations3.8 Power Grid Design Synthesis – ESD Design Rule Checking Methods3.9 Summary and Closing CommentsReferences
Chapter 4: ESD Power Clamps
4.1 ESD Power Clamps4.2 Design Synthesis of ESD Power Clamps4.3 Design Synthesis of ESD Power Clamp – The ESD Power Clamp Shunting Element4.4 ESD Power Clamp Issues4.5 ESD Power Clamp Design4.6 ESD Power Clamp Design Synthesis – Bipolar ESD Power Clamps4.7 Master/Slave ESD Power Clamp Systems4.8 Summary and Closing CommentsReferences
Chapter 5: ESD Signal Pin Networks Design and Synthesis
5.1 ESD Signal Pin Structures5.2 ESD Input Structures – ESD and Bond Pads Layout5.3 ESD Design Synthesis and Layout of MOSFETs5.4 ESD Design Synthesis and Layout of Diodes5.5 ESD Design Synthesis of SCRs5.6 ESD Design Synthesis and Layout of Resistors5.7 ESD Design Synthesis of Inductors5.8 Summary and Closing CommentsReferences
Chapter 6: Guard Ring Design and Synthesis
6.1 Guard Ring Design and Integration6.2 Guard Ring Characterization6.3 Semiconductor Chip Guard Ring Seal6.4 I/O to Core Guard Rings6.5 I/O to I/O Guard Rings6.6 Within I/O Guard Rings6.7 ESD Signal Pin Guard Rings6.8 Library Element Guard Rings6.9 Mixed-Signal Guard Rings – Digital to Analog6.10 Mixed-Voltage Guard Rings – High Voltage to Low Voltage6.11 Passive and Active Guard Rings6.12 Trench Guard Rings6.13 TSV Guard Rings6.14 Guard Ring DRC6.15 Guard Rings and Computer Aided Design Methods6.16 Summary and Closing CommentsReferences
Chapter 7: ESD Full-Chip Design Integration and Architecture
7.1 Design Synthesis and Integration7.2 Digital Design7.3 Custom Design vs. Standard Cell Design7.4 Memory ESD Design7.5 Microprocessor ESD Design7.6 Application-Specific Integrated Circuits7.7 CMOS Image Processing Chip Design7.8 Mixed-Signal Architecture7.9 Summary and Closing CommentsReferences
Index

Content preview from ESD: Design and Synthesis

Chapter 2

ESD Architecture and Floorplanning

2.1 ESD Design Floorplan

One of the most fundamental issues and challenges in the ESD design discipline is ESD architecture and floorplanning. The integration of the devices, circuits, sub-functions, and cores is critical to the success of EOS and ESD robust designs. In each application space, the floorplan and layout of a semiconductor chip may be different, leading to unique challenges for ESD protection design [1–6]. Whether it is DRAM [10–12], SRAM [1–3, 6], NVRAM, microprocessor [1–4, 12–20], CPU, ASICs [1–6], or semiconductor foundry, each has unique challenges for ESD design. Whether it is single voltage, mixed voltage or mixed signal, the ESD design strategy and architecture has to be modified. Additionally, CMOS, BiCMOS, and BCD technology produce digital [1–20], analog [21–24], power [25–29], and RF [30–32] applications with integration, layout, and design.

In this text, one of the goals is to teach how to construct a semiconductor chip to achieve an ESD robust implementation. Significant focus in publications address semiconductor device physics and ESD circuits, but the subject of how to integrate all the elements into a given product has limited exposure.

The ordering of materials in this text is constructed in the fashion that a semiconductor chip is assembled. In this chapter, we will begin by discussing the architecture and layout floorplanning for different chip architectures. The discussion will address both peripheral ...

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ESD: Design and Synthesis

by Steven H. Voldman

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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