Chapter 2
ESD Architecture and Floorplanning
2.1 ESD Design Floorplan
One of the most fundamental issues and challenges in the ESD design discipline is ESD architecture and floorplanning. The integration of the devices, circuits, sub-functions, and cores is critical to the success of EOS and ESD robust designs. In each application space, the floorplan and layout of a semiconductor chip may be different, leading to unique challenges for ESD protection design [1–6]. Whether it is DRAM [10–12], SRAM [1–3, 6], NVRAM, microprocessor [1–4, 12–20], CPU, ASICs [1–6], or semiconductor foundry, each has unique challenges for ESD design. Whether it is single voltage, mixed voltage or mixed signal, the ESD design strategy and architecture has to be modified. Additionally, CMOS, BiCMOS, and BCD technology produce digital [1–20], analog [21–24], power [25–29], and RF [30–32] applications with integration, layout, and design.
In this text, one of the goals is to teach how to construct a semiconductor chip to achieve an ESD robust implementation. Significant focus in publications address semiconductor device physics and ESD circuits, but the subject of how to integrate all the elements into a given product has limited exposure.
The ordering of materials in this text is constructed in the fashion that a semiconductor chip is assembled. In this chapter, we will begin by discussing the architecture and layout floorplanning for different chip architectures. The discussion will address both peripheral ...
