April 2011
Intermediate to advanced
290 pages
8h 7m
English
Chapter 3
ESD Power Grid Design
3.1 ESD Power Grid
The ESD power grid and metal interconnects have a significant impact on the ESD robustness of the semiconductor chip [1–3]. In the ESD design synthesis, it is important to integrate the interconnects, vias, and power grid effectively with the bond pads, the circuitry, ESD signal pin devices, and ESD power clamp circuitry [2, 3]. In this chapter, the ESD design synthesis of the interconnects and the power grid will be discussed. The discussion will address both practical and analytical examples [1–28].
3.1.1 ESD Power Grid – Key ESD Design Parameters
In the ESD design synthesis of the power grid, there are key ESD design parameters and metrics to consider. These key parameters are to be considered as part of the ESD design synthesis of the power grid:
- Bus Width: The bus width required to survive ESD failure for a given metal layer.
- Bus Resistance: The bus resistance per unit length.
- Across ESD Bus Resistance: The bus resistance across the length of the ESD network.
- Critical Bus Resistance: The worst case bus resistance allowed without failure of the signal pin (can be defined as the breakdown voltage at the signal pin divided by the ESD current through the power bus).
- ESD Signal Pin to ESD Power Clamp Distance: The distance between the ESD signal pin and the ESD power clamp.
- Critical ESD Signal to ESD Power Clamp Resistance: The worst case resistance between the ESD signal pin and the ESD power clamp prior to signal pin failure. ...
