ESD Full-Chip Design Integration and Architecture
7.1 Design Synthesis and Integration
ESD protection is fundamental to semiconductor chip design [1–5]. In this chapter, examples of ESD design synthesis and integration will be discussed for different chip designs. The chapter will begin by discussing architectures for memory [6–21], microprocessors [22–42], ASIC standard cell [43–49], analog and radio frequency [50–59]. The sections will provide examples of digital, analog, RF, mixed-signal, and mixed-voltage interface chip integration and architectures.
7.2 Digital Design
ESD design synthesis in digital design typically does not require co-synthesis of the ESD solutions and the digital circuitry for digital design applications below 1 GHz [1–49]. But, the ESD design synthesis must be integrated into the floorplan of a semiconductor chip.
Integration of the ESD networks is built into the architecture of the chip to ensure achieving ESD protection for all pin combinations specified in the ESD standards. ESD protection must be provided between signal pins and power rails, power rail-to-power rails, and pin-to-pin. In semiconductor designs, circuitry interfacing with other semiconductor chips or systems can be at the same voltage or different voltage levels. Peripheral circuits and power rails are separated from internal core circuitry and other sensitive functions. Guard rings are placed to minimize interaction and injection between the different chip domains. To address ...