The text ESD: Design and Synthesis is targeted at the semiconductor chip “architect”, team lead floorplan engineer, circuit designer, design layout support, ESD engineer, and computer aided design (CAD) integration team. In this text, a balance is established between design synthesis, design integration, layout engineering, and design checking and verification.
The first goal of the text ESD: Design and Synthesis is to teach the “art” of ESD chip design for a semiconductor chip.
The second goal is to demonstrate a step-by-step process to provide ESD protection to a semiconductor chip. The flow of the text addresses floorplanning, architecture, power rails, ESD networks for power rails, ESD signal pin solutions, guard rings, and examples of implementations. This flow is significantly different from the approach taken in most texts, but is the actual flow of how a design team proceeds through the ESD implementation.
The third goal is to expose the reader to the growing number of architectures and concepts being discussed today. Examples of DRAM, SRAM, image processing chips, microprocessors, mixed-voltage to mixed-signal applications, and floorplans will be shown.
The fourth goal is to address topics that are not discussed in other ESD textbooks. These topics include power bus architecture, guard rings, and floorplanning. For many ESD engineers and circuit designers, this is common knowledge; for others, it is not. A significant part of the ESD design and synthesis is spent ...