ESD

6Analog-to-Digital ESD Design Synthesis

6.1 Digital and Analog

In mixed-signal chips, analog and digital functions are isolated into functional blocks to reduce noise coupling between the digital circuitry and analog functions. The switching noise of the digital circuitry must be isolated to avoid analog functional failures. Figure 6.1 shows an example of a semiconductor chip with separated digital and analog domains. Semiconductor chip architectures today provide the following solutions: (i) separate digital and analog circuit domains, (ii) separate digital and analog V_DD power rails, (iii) separate digital V_SS (DV_SS) and analog V_SS (AV_SS) power rails, (iv) an ESD power clamp for each independent domain, and (v) a bidirectional symmetric diode string between DV_SS and AV_SS.

Figure 6.1 Digital and analog domains.

In the ESD design synthesis process, there is a flow of steps and procedures to construct a semiconductor chip. The following design synthesis procedure is an example of an ESD design flow needed for semiconductor chip implementations:

• I/O, domains, and core floor plan: Define floor plan of regions of cores, domains, and peripheral I/O circuitry.
• I/O floor plan: Define area and placement for I/O circuitry.
• ESD signal pin floor plan: Define ESD area and placement.
• ESD power clamp network floor plan: Define ESD power clamp area and placement for a given domain.
• ESD domain-to-domain ...