10.1 Latchup in Analog Applications
CMOS latchup is a concern in advanced semiconductor CMOS, BiCMOS, and bipolar–CMOS–LDMOS (BCD) technologies within a given circuit, between adjacent circuits, and between domains [1–59]. Due to technology scaling, the physical distances between p-channel MOSFETs and n-channel MOSFETs continue to be reduced in the periphery and core of circuits. With density scaling, the number of I/O circuits increases according to Rent’s rule. As a result, the aspect ratio of peripheral I/O circuitry continues to move toward “long/narrow I/O standard cells” with decreased spacing between adjacent I/O standard cells. Hence, the interaction between adjacent I/O (e.g., I/O to I/O) will continue to be a design issue associated with CMOS latchup. In addition, with mixed signal (MS) and system on chip (SOC), the placement of circuits of different domains can also lead to CMOS latchup concerns.
Figure 10.1 shows possible latchup issues in a semiconductor chip. The focus in this chapter will be on the issue of I/O-to-I/O latchup [6, 7], guard rings [8–18], through-silicon via (TSV) [32–39], deep trench [40–46], and active guard rings [47–59]. Test structures that address I/O-to-I/O interactions will be discussed. Electrical measurements of parasitic bipolar current gain and analysis will be shown.