Evolving Networking Technologies

12Synthesis and Analysis of Digital IIR Filters for Denoising ECG Signal on FPGA

Seema Nayak¹, Manoj Nayak², Shamla Matri³, Kanta Prasad Sharma⁴

¹ Department of Electronics and Communication Engineering, IIMT College of Engineering, Greater Noida, India

² Manav Rachna International Institute of Research and Studies Faridabad, India

³ School of Computer engineering and Technology, MIT-WPU, Pune, India

⁴Computer Science and Engineering, GLA University Mathura, India

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Abstract

In recent years, field-programmable gate arrays have progressively become vital for creating the means for every type of digital system design due to their compact growth point and lower expense. Moreover, their flexibility has enabled growth in the field and made hardware compatible with runtime environment. This chapter focuses on a new, simple and well-organized approach for synthesis design of optimal order IIR digital filters to reduce noise in ECG signal on FPGA. A summary of its resource consumption (amount of slice, slice flip-flops figure, number of 4-input LUTs, figure of bonded IOBs, number of BUFG and DSP48A1 slice), the timing (smallest amount of input arrival time sooner than clock [set-up time] and maximum output requisite period subsequent to clock [hold time] and power consumed are presented after synthesis and simulation. This is achieved by conversion of MatLab code of different designed IIR digital filters for denoising ECG signal into Verilog code using ...