Explainable Machine Learning Models and Architectures

5Synthesis and Time Analysis of FPGA-Based DIT-FFT Module for Efficient VLSI Signal Processing Applications

Siba Kumar Panda¹*, Konasagar Achyut² and Dhruba Charan Panda³

¹Xeedo Technologies Pvt Ltd, Bangalore, India

²J.B. Institute of Engineering & Technology, Hyderabad, India

³Department of Electronics Science, Berhampur University, Odisha, India

Abstract

Now is the era of high-speed processors with reconfigurable architectures. The dedicated architectures have a wide variety of applications in signal processing, image processing, and audio/video processing provinces. Further implementation of those dedicated architectures in FPGA/ASIC level plays an important role. Synthesis and static timing analysis of FPGA-based Decimation in Time Fast Fourier Transform (DIT-FFT) architecture for VLSI signal processing application is presented in this chapter. This work presents a continuous flow such as RTL design, simulation, synthesis, and implementations as well as timing investigation of the designed module. The architecture is designed and verified for different values of N and converted to corresponding gate level netlist using synthesis. Post-synthesis, utilization and power report are recorded. The post-implementation and timing confirm that the design for N=8 consumes 780 LUTs (logic), 257 registers (BRAMs), 0.163Won-chip power, set up slack 3.258ns, hold slack 0.430ns with timing cohesively meeting at 24ns. Post-timing analysis, physical layout of the designed circuit with ...