July 2015
Intermediate to advanced
408 pages
11h 7m
English
Content preview from Formal Verification
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Chapter 8
Formal equivalence verification
In this chapter we describe Formal Equivalence Verification (FEV), an FV technique focused on checking whether two designs are logically equivalent. There are several ways we can define equivalence for FEV tools: combinational equivalence, which optimizes the problem by breaking up models at latch/flop boundaries; sequential equivalence, which checks that behavior of two models over a period of time results in equivalent outputs; and transactional equivalence, which checks that certain well-defined operations produce identical results on two models. We then discuss how these types of equivalence fit into some common real design flows: using RTL-RTL equivalence to check design changes or optimizations, ...
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I wanted to learn C and C++, but it didn't click for me until I picked up an O'Reilly book. When I went on the O’Reilly platform, I was astonished to find all the books there, plus live events and sandboxes so you could play around with the technology.Addison B.
I’ve been on the O’Reilly platform for more than eight years. I use a couple of learning platforms, but I'm on O'Reilly more than anybody else. When you're there, you start learning. I'm never disappointed.Amir M.
I'm always learning. So when I got on to O'Reilly, I was like a kid in a candy store. There are playlists. There are answers. There's on-demand training. It's worth its weight in gold, in terms of what it allows me to do.