Detailed FPGA Implementation Issues
The previous chapters have set the scene in terms of background to DSP and computer arithmetic, and then in the last two chapters, the various implementation technologies have been highlighted; Chapter 4 has highlighted the wider range of technologies and Chapter 5 has described, in a little more detail, the various FPGA offerings. The remaining chapters now describe the issues for implementing complex DSP systems onto heterogeneous platforms, or even a single FPGA device. This encompasses considerations such as selection of the suitable model for DSP system implementation, partitioning of DSP complexity into hardware and software, mapping of DSP functions efficiently onto FPGA hardware, development of a suitable memory architecture, and achievement of design targets in terms of throughput, area and energy. However, it is imperative that the reader understands the detailed FPGA implementation of DSP functionality in order that this process is inferred correctly at both the system partitioning and circuit architecture development stages.
At the system partitioning level, for example, it may become clear that the current system under consideration will consume more than the dedicated multiplicative resources available. The designer is then faced with a number of options, either to restrict the design space so that the design mapping ensures that only the dedicated multiplier resources are used, or alternatively, to map the design ...