Architecture Derivation for FPGA-based DSP Systems
The technology review, Chapters 4 and 5, clearly demonstrated the need to develop a circuit architecture when implementing DSP algorithms on silicon hardware, whether the platform is ASIC or FPGA technology. The circuit architecture allows the performance needs of the application to be captured effectively. As was highlighted earlier, it is possible to implement high levels of parallelism available in the FIR filter expression (Equation 2.11 in Chapter 2), in order to achieve a performance increase, or to pipeline the SFG or dataflow graph (DFG) heavily. The first realization assumes that the hardware resource is available in terms of silicon area and the second approach assumes that the increased latency in terms of clock cycles, incurred as a result of the pipelining (admittedly at a smaller clock period), can be tolerated. It is clear that optimizations made at the hardware level can have direct cost implications for the resulting design. Both of these aspects can be captured in the circuit architecture.
As described in Chapter 5, this trade-off is much easier to explore in ‘fixed architectural’ platforms such as microprocessors, DSP processors or even reconfigurable processors, as sufficiently appropriate tools can, or have been developed to map the algorithmic requirements efficiently onto the available hardware. As already discussed, the main attraction of using FPGAs is that the high level of available ...