book

FPGA-based Implementation of Signal Processing Systems, 2nd Edition

by Roger Woods, John McAllister, Gaye Lightbody, Ying Yi

May 2017

Intermediate to advanced

360 pages

11h 42m

English

Wiley

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1.1 Introduction1.2 Field Programmable Gate Arrays1.3 Influence of Programmability1.4 Challenges of FPGAsBibliography
2.1 Introduction2.2 Definition of DSP Systems2.3 DSP Transformations2.4 Filters2.5 Adaptive Filtering2.6 Final CommentsBibliography
3.1 Introduction3.2 Number Representations3.3 Arithmetic Operations3.4 Alternative Number Representations3.5 Division3.6 Square Root3.7 Fixed-Point versus Floating-Point3.8 ConclusionsBibliography
4.1 Introduction4.2 Implications of Technology Scaling4.3 Architecture and Programmability4.4 DSP Functionality Characteristics4.5 Microprocessors4.6 DSP Processors4.7 Graphical Processing Units4.8 System-on-Chip Solutions4.9 Heterogeneous Computing Platforms4.10 ConclusionsBibliography
5.1 Introduction5.2 Toward FPGAs5.3 Altera Stratix® V and 10 FPGA Family5.4 Xilinx UltrascaleTM/Virtex-7 FPGA families 5.5 Xilinx Zynq FPGA Family5.6 Lattice iCE40isp FPGA Family5.7 MicroSemi RTG4 FPGA Family5.8 Design Stratregies for FPGA-based DSP Systems5.9 ConclusionsBibliography
6.1 Introduction6.2 FPGA Functionality6.3 Mapping to LUT-Based FPGA Technology6.4 Fixed-Coefficient DSP6.5 Distributed Arithmetic6.6 Reduced-Coefficient Multiplier6.7 ConclusionsBibliography
7.1 Introduction7.2 High-Level Synthesis7.3 Xilinx Vivado7.4 Control Logic Extraction Phase Example7.5 Altera SDK for OpenCL7.6 Other HLS Tools7.7 ConclusionsBibliography
8.1 Introduction8.2 DSP Algorithm Characteristics8.3 DSP Algorithm Representations8.4 Pipelining DSP Systems8.5 Parallel Operation8.6 ConclusionsBibliography

9.1 Introduction9.2 Motivation for Design for Reuse9.3 Intellectual Property Cores9.4 Evolution of IP cores9.5 Parameterizable (Soft) IP Cores9.6 IP Core Integration9.7 Current FPGA-based IP cores9.8 Watermarking IP9.9 SummaryBibliography
10.1 Introduction10.2 Dataflow Modeling of DSP Systems10.3 Architectural Synthesis of Custom Circuit Accelerators from DFGs10.4 Model-Based Development of Multi-Channel Dataflow Accelerators10.5 Model-Based Development for Memory-Intensive Accelerators10.6 SummaryNotesBibliography
11.1 Introduction to Adaptive Beamforming11.2 Generic Design Process11.3 Algorithm to Architecture11.4 Efficient Architecture Design11.5 Generic QR Architecture11.6 Retiming the Generic Architecture11.7 Parameterizable QR Architecture11.8 Generic Control11.9 Beamformer Design Example11.10 SummaryBibliography
12.1 Introduction12.2 Big Data12.3 Big Data Analytics12.4 Acceleration12.5 k-Means Clustering FPGA Implementation12.6 FPGA-Based Soft Processors12.7 System Hardware12.8 ConclusionsBibliography
13.1 Introduction13.2 Sources of Power Consumption13.3 FPGA Power Consumption13.4 Power Consumption Reduction Techniques13.5 Dynamic Voltage Scaling in FPGAs13.6 Reduction in Switched Capacitance13.7 Final CommentsBibliography
14.1 Introduction14.2 Evolution in FPGA Design Approaches14.3 Big Data and the Shift toward Computing14.4 Programming Flow for FPGAs14.5 Support for Floating-Point Arithmetic14.6 Memory ArchitecturesBibliography

Content preview from FPGA-based Implementation of Signal Processing Systems, 2nd Edition

3 Arithmetic Basics

3.1 Introduction

The choice of arithmetic has always been a key aspect for DSP implementation as it not only affects algorithmic performance, but also can impact system performance criteria, specifically area, speed and power consumption. This usually centers around the choice of a floating-point or a fixed-point realization, and in the latter case, a detailed study is needed to determine the minimal wordlength needed to achieve the required performance. However, with FPGA platforms, the choice of arithmetic can have a much wider impact on the performance as the system designer can get a much more direct return from any gains in terms of reducing complexity. This will either reduce the cost or improve the performance in a similar way to an SoC designer.

A key requirement of DSP implementations is the availability of suitable processing elements, specifically adders and multipliers; however, many DSP algorithms (e.g. adaptive filters) also require dedicated hardware for performing division and square roots. The realization of these functions, and indeed the choice of number systems, can have a major impact on hardware implementation quality. For example, it is well known that different DSP application domains (e.g. image processing, radar and speech) can have different levels of bit toggling not only in terms of the number of transitions, but also in the toggling of specific bits (Chandrakasan and Brodersen 1996). More specifically, the signed bit in speech ...