FPGA-based Implementation of Signal Processing Systems, 2nd Edition

7 Synthesis Tools for FPGAs

7.1 Introduction

In the 1980s, the VHSIC program was launched which was a major initiative to identify the need for high-level tools for the next generation of integrated circuits. From this the VHDL language and associated synthesis tools were developed; these were seen as a step function for the design of integrated circuits and, until recently, represented the key design entry mechanism for FPGAs. To avoid the high license costs which would act to prevent FPGA users from using their technology, each of the main vendors developed their own tools.

To a great extent, though, this has strengthened the view of FPGAs as a hardware technology, something that is viewed as difficult to program. For this reason, we have seen a major interest in developing high-level synthesis (HLS) tools to make this a more easily programmable technology for software developers. Xilinx has launched the Vivado tools which allow users to undertake C-based synthesis using Xilinx FPGA technology. Altera have developed an approach based on OpenCL, called SDK for Open Computing Language, which allows users to exploit the parallel version of C, developed for GPUs.

A number of other tools have been developed, including C-based synthesis tools both in the commercial (Catapult^® and Impulse-C) and academic (GAUT, CAL and LegUp) domain with some focus on FPGA, and higher-level tools such as dataflow-based synthesis tools. The tools that have been chosen and described in this chapter ...