FPGAs 101

5.6.5. Simulation Phase Outputs

The output is shown as a waveform for this testbench. The full simulation waveform that results from applying the input stimulus defined in the testbench is shown in Figure 5-10. The full simulation view is difficult to read, so the expanded view of test case 1, test case 4, and test case 14 are presented in this section.

Figure 5-10. Full Simulation View

(Material based on or adapted from figures and text owned by Xilinx, Inc., courtesy of Xilinx, Inc. Copyright Xilinx © 1995–2008 used in Xilinx ISE WebPack™ software version 10.1.)

Lines 70–72. Test Case 1

P1 pulse goes high at 200.00 nsec, then low at 850.00 ...