5.6.6. Automatic Testbench
An automatic testbench can make design verification easier. However, if your automatic testbench is not complete or correct, the results can be misleading, in that you may be searching for errors in the design when in reality they are in the testbench. With an automatic testbench, you are not required to manually view or verify the output. This type of testbench is designed to evaluate the output results and provide the final results.
However, just like anything else, you have to make sure that this testbench is reporting accurate information. Otherwise, the results can be wrong. The manual testbench has been modified to write the test results to an external file. The output file should contain whatever information ...
Get FPGAs 101 now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
