FPGAs 101

Chapter 7. Implementation

7.1. Introduction

Implementation, also referred to as place and route (PAR), is the phase in FPGA development where the design has been synthesized and an RTL simulation performed (at least I hope), and maybe a functional simulation. The design is no longer at a high level but is a mid-level netlist format created by the synthesis process. This is the development process that produces a bit stream file. Implementation can be very time intensive, because so many elements must be considered, decisions made, and potential issues to resolved. Some designs are implemented with ease, while others can take days to complete. In my opinion, the implementation tool has the hardest job of all the development process tools. So ...