FPGAs: Instant Access

Chapter 7. Using Design Tools

In an Instant

• Simulation Tools
  • Event-driven Logic Simulators
  • Logic Values and Different Logic Value Systems
  • Mixed-language Simulation
  • Alternative Delay Formats
  • Cycle-based Simulators
  • Choosing a Logic Simulator
• Synthesis (Logic/HDL versus Physically Aware)
  • Logic/HDL Synthesis Technology
  • Physically Aware Synthesis Technology
  • Retiming, Replication, and Resynthesis
• Timing Analysis
  • Static Timing Analysis
  • Statistical Static Timing Analysis
• Verification in General
  • Verification IP
  • Verification Environments and Creating Testbenches
  • Analyzing Simulation Results
• Formal Verification
  • Different Flavors of Formal Verification
  • Terminology and Definitions
  • Alternative Assertion/Property Specification Techniques