From ASICs to SOCs: A Practical Approach

PowerTheater Analyst

PowerTheater Analyst, built with proven Watt Watcher technology, represents a superior alternative to tedious and error-prone manual methods, such as spreadsheet analysis, as well as gate- and transistor-level methods which require the design to be synthesized in pieces and then simulated at very detailed levels of abstraction. Using this capability at both RT and gate level, designers can perform detailed power analysis for the entire chip or any set of sub-blocks, including memory, I/O, logic, and clock trees. Peak and time-based power is reported on a user-defined time interval, down to the Verilog or VHDL simulation resolution. PowerTheater Analyst addresses issues such as power bus sizing, electromigration, and reliability ...