From ASICs to SOCs: A Practical Approach

5.3. Low-Power Design Techniques and Methodologies

Low-power techniques vary depending on the level of the design targeted, ranging from semiconductor technology to the higher levels of abstraction. These abstraction levels are classified as algorithm, architecture, RT, gate, and transistor levels. Figure 5.4 shows various levels of hierarchy that should be considered for low-power designs.

Figure 5.4. Levels of Design Power Optimization

The higher levels of design abstraction shown in Figure 5.4 provide larger amounts of power reduction for chip designs. In higher levels of abstraction, such as algorithm level, designers have a greater degree ...