From ASICs to SOCs: A Practical Approach

5.5. Tips and Guidelines for Low-Power Design

The goal of this section is to summarize the tips and guidelines for low-power design of ASICs and SOCs.

• The most effective power-optimization techniques are the higher level ones. These are algorithmic and architectural optimization techniques.

• Use low-power process and libraries. There are low-power standard cell libraries for 0.18 µm such as Xemics CooLib. (Refer to reference 16 for more information.) The low-power libraries should be used in conjunction with a low-power process that is available from most ASIC vendors.

• Decrease the dynamic power by reducing all of the terms in the fundamental equation of power:

• Apply the following for your supply voltages:

  Lower the supply voltage for the entire ...