Describing Combinational and Sequential Logic using Verilog HDL


We have already come across numerous examples in the previous chapters of Verilog designs written in the so-called data-flow style. This style of description makes use of the parallel statement known as a continuous assignment. Predominantly used to describe combinational logic, the flow of execution of continuous assignment statements is dictated by events on signals (usually wires) appearing within the expressions on the left- and right-hand sides of the continuous assignments. Such statements are identified by the keyword assign. The keyword is followed by one or more assignments terminated by a semicolon.

All of the following examples describe combinational logic, this being the most common use of the continuous assignment statement:

//some continuous assignment statements
   assign A = q [0], B = q [1], C = q [2];

   assign out = (~s1 & ~s0 & i0) |
       (~s1 & s0 & i1) |
       (s1 & ~s0 & i2) |
       (s1 & s0 & i3);

  assign #15 {c_out, sum} = a + b + c_in;

The continuous assignment statement forms a static binding between the wire being assigned on the left-hand side of the = operator and the expression on the right-hand side of the assignment operator. This means that the assignment is continuously active and ready to respond to any changes to variables appearing in the right-hand side expression (the inputs). Such changes result in the evaluation of the ...

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