In Chapters 1–5, state machines have been implemented using the equations obtained from the state diagram. This approach ensures that the logic for the state machine is under complete control of the designer.
However, if the state machine is implemented using behavioural mode, the Verilog compiler will optimize the design.
There is a very close relationship between the state diagram and the behavioural Verilog description that allows a direct translation from the state diagram to the Verilog code.
In this system there are two inputs: s to start the system and x to choose either single-pulse or multiple-pulse mode. In single-pulse mode, the L ouput is used to indicate to the user that a single pulse has been generated. In multiple-pulse mode, L is suppressed. Figure D.1 illustrates the state diagram for this system.
// Behavioural State Machine. module pulsar(s,clk,rst,P,L,ab); 1 input s,clk,rst; 2 output [1:0]ab,P,L; 3 reg[1:0]state, P, L; 4 parameter s0=2′ b00, s1=2′ b01, s2=2′ b11, s3=2′ b10; // now define state sequence for FSM (from state diagram). 5 always @ (posedge clk or negedge rst) 6 if (~rst) 7 state <= s0;