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Future Trends in Microelectronics: Up the Nano Creek by Alex Zaslavsky, Jimmy Xu, Serge Luryi

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Physical Limits of Silicon CMOS:Real Showstopper or Wrong Problem?

M. Brillouët

CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, France

1. Introduction

Digital information processing has become a key driver for the growth of the world economy. It has been fueled by the progress of microelectronics that is usually described by an exponential growth of some performance metric, often named Moore’s Law. Actually, the early papers of Gordon Moore1-3 only stressed the continuing search for a higher integration density of circuits, mostly through feature size reduction, while their electrical behavior was not even mentioned. It was not until the mid-1970’s that Robert Dennard formalized the benefits of downscaling device dimension:4 the present paradigm that miniaturization makes integrated circuits denser, faster, less power-hungry, cheaper and more reliable was born. The question then is how long will this trend last?

For more than two decades, technical papers announced the imminent dismissal of Si CMOS technology, stressing first the 1 μm barrier, then the 100 nm brick walls, and recently the 10 nm limit: to date they all proved to be wrong. After looking at some similar claims, we will focus on the so-called physical limits of the processing unit, trying to outline the underlying assumptions of such assertions and their possible shortcomings.

Assuming that classical Si CMOS will encounter some practical limits in the future, the latest version of the ITRS roadmap gives a thorough analysis ...

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