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Future Trends in Microelectronics: Up the Nano Creek by Alex Zaslavsky, Jimmy Xu, Serge Luryi

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Scaling Limits of Silicon CMOS and Non-Silicon Opportunities

Y. Nishi

Dept. of Electrical Engineering, Stanford University, Stanford, CA 94305, U.S.A.

1.    Introduction

As we look at the future of silicon based CMOS, it is becoming more difficult to be as optimistic as we used to be. A variety of problematic issues and, more importantly, the magnitude of anticipated challenges, may not be as easy to circumvent as those we have successfully overcome over the past two decades. Not only difficulties in cost-effective processing equipment and process parameter controls, but also perceived limits in device operation improvement itself will pose more problems than in the past. Rapidly increasing MOSFET leakage currents at the gate, source, and drain terminals, and the diminishing improvement in the drive current with reduced channel length are now pushing us to consider alternative materials for the channel of MOSFETs. At the integration level, the interconnect delay that has been identified as the stumbling block for large high-performance chips will certainly become worse, coupled with power consumption and heat dissipation management challenges. As we will have more areas dedicated to high-speed embedded memory, mostly consisting of static random access memory (SRAM), memory standby power will become a major problem, especially with MOSFETs operated at a much lower ION/IOFF ratio than they used to be. Furthermore, general trends for system-on-a-chip design driven by significant ...

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