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Future Trends in Microelectronics: Up the Nano Creek by Alex Zaslavsky, Jimmy Xu, Serge Luryi

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Ultimate VLSI Clocking Using Passive Serial Distribution

M. Banu and V. Prodanov

MHI Consulting LLC, Murray Hill, NJ 07974, U.S.A.

1.  Introduction

The quest for absolutes is perhaps as old as scientific thought. As a popular tradition goes, thousands of years ago Archimedes recognized the great value of a reference by his celebrated observation that he could move the Earth if given a fixed point. In the modern age, an arguably even more powerful feat, the development of advanced digital machines, was made possible by designing massive synchronous logic switching in unison to the beat of a global timing reference: the system clock. The machine miniaturization into VLSI chips followed the same approach.

In the beginning of the VLSI era, when the chips were still small by today’s standards and the system clock was running at sub- and low-MHz speeds, the practical realization of the timing backbone was relatively easy. The initial VLSI design methodology treated timing almost as an afterthought. As the chips got much larger and the clock speed increased to the GHz range, the correct logic timing became increasingly difficult, to the point of turning into a major design bottleneck. Currently, highly-specialized engineering teams helped by proprietary sophisticated computer programs labor long hours to configure clock distribution solutions known as “timing trees”, which are customized and fine-tuned for every particular VLSI chip. The typical end result is a highly complex clocking ...

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