Future Trends in Microelectronics: Up the Nano Creek

Quasiballistic Transport in Nano-MOSFETs

E. Sangiorgi, S. Eminente, C. Fiegna

IU.NET and ARCES-DEB, University of Bologna, Bologna, Italy

P. Palestri, D. Esseni, and L. Selmi

IU.NET and DIEGM, University of Udine, Udine, Italy

1.   Introduction

The International Roadmap for Semiconductors has predicted that starting from the 45 nm technology node, an increase in the basic transport properties (called a “ballistic technology booster”) must be achieved to reach the target specifications of high-performance devices¹. The on-current I_ON of the MOSFETs is limited to a maximum value I_BL that is reached in the ballistic transport regime.^2,3 Hence, improvements in I_ON demand an increase of either I_BL or of the ballisticity ratio BR defined as I_ON/I_BL, which is a metric of how close I_ON comes to the ballistic limit. In recent technologies, the observed BR values have not significantly improved⁴ and are thought to have only a modest dependence on the technology node (TN) and on the gate length L_G for conventional silicon MOSFETs. Further improvements in I_BL requires ultra-thin silicon-on-insulator (SOI) with silicon thickness below 10 nm or non-conventional channel compsition.⁵

In this chapter we extend previous analyses on the role of scattering in the channel and drain of decananometer MOSFETs and our results demonstrate that, for the explored gate lengths values L_G, scattering still holds I_ON far below the ballistic limit.^6,7

Accurate modeling of MOSFETs with L_G comparable to or shorter ...