Emerging Nanotechnology for Integration of Nanostructures in Nanoelectronic Devices

T. Baron, C. Agraffeil, F. Dhalluin, M. Kogelschtaz, G. Cunge, T. Chevolleau, B. Salem, B. Salhi, H. Abed, A. Potié, L. Latu-Romain, C. Ternon, K. Aissou

Labo. des Technologies de la Microélectronique, CNRS & Univ. Joseph Fourier 17 Rue des Martyrs, F38054 Grenoble, France

L. Montés

IMEP-LAHC/Minatec, Grenoble-INP, 3 parvis Louis Neel, Grenoble, France

P. Mur, G. Molas, B. De Salvo, E. Jalaguier, T. Ernst, P. Ferret

CEA-LETI/Minatec, 17 Rue des Martyrs, F38054 Grenoble, France

P. Gentile and N. Pauc

CEA-INAC/SiNaPS, 17 Rue des Martyrs, F38054 Grenoble, France

1.   Introduction

Scaling down of semiconductor devices is the driving force for the development of new applications (mobile phone, memory cards, sensors, etc.). Up to now, device downscaling has been enabled by the top-down approach, combining lithography and etching technologies. However, we will soon reach the limitation of this approach to form nanostructures with uniform properties. In this context, the bottom-up approach, i.e. elaborating nanostructures in a self-ordered manner and integrating them directly into devices, seems to be a promising way to push towards miniaturization of microelectronics components and to create new functionalities.1

In this chapter, we will focus our attention on two emerging nanotechnologies we have developed to fabricate, organize and integrate nanomaterials (nanodots, nanowires) in nanoelectronics devices. ...

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