Future Trends in Microelectronics: From Nanophotonics to Sensors to Energy

Silicon for Spintronic Applications: Strain-Enhanced Valley Splitting

V. Sverdlov, O. Baumgartner, T. Windbacher, and S. Selberherr

Institute for Microelectronics, TU Wien Gußhausstraße 27-29/E360, A-1040 Wien, Austria

1.   Introduction

The rapid increase in computational power and speed of integrated circuits is supported by the incessant downscaling of semiconductor devices. Thanks to constantly introduced innovative changes in the technological processes, the miniaturization of MOSFETs epitomized by Moore’s Law successfully continues. The recently introduced 32 nm technology¹ involves improved high-κ gate stack dielectrics integrated with metal gates. These advances, first introduced for the 45 nm MOSFET process technology by Intel,² represent some of the major changes in the technological processing since the invention of MOSFETs. Although alternative channel materials with mobility higher than in silicon have already been investigated,^3,4 it is believed that silicon will remain the main channel material for MOSFETs beyond the 32 nm technology node.

With scaling apparently approaching its fundamental limits, the semiconductor industry is facing critical challenges. New engineering solutions and innovative techniques are required to improve CMOS device performance. Strain-induced mobility enhancement, first introduced for the 90 nm technology node, is now routinely used to increase the device performance. With the 4th generation of stressors employed in the 32nm node,¹ strain ...