Future Trends in Microelectronics

1.4

Three-Dimensional Integration of Ge and Two-Dimensional Materials for One-Dimensional Devices

M. Östling, E. Dentoni Litta and P.-E. Hellström

School of Information and Communication Technology, KTH Royal Institute of Technology, 16440 Kista, Sweden

1 Introduction

The outstanding progress experienced by the semiconductor industry, and the electronics and information technology industries as a consequence, in the past decades is aptly represented by the well-known Moore's Law,¹ which states that the number of components that can be manufactured on a chip at the same cost has increased exponentially over time. Traditionally, Moore's Law has been supported by two-dimensional (2D) scaling, initially captured by Dennard's scaling rules² but recently complemented by the continuous introduction of novel technologies and device structures, such as Cu/low-κ back end of line (BEOL),³ strain engineering,⁴ high-κ/metal gate,⁵ channel engineering,⁶ fully depleted silicon-on-insulator (FD-SOI),⁷ and fin-FETs,⁸ as well as by the introduction of increasingly complex multiple patterning techniques⁹ – see Fig. 1. However, continued 2D scaling of complementary metal-oxide-semiconductor (CMOS) technology past the 7 nm node looks extremely complex for technical and economic reasons, as well as fundamental physical limits. Complex technical issues make it extremely challenging to achieve both area scaling and the expected performance improvements, due to the increased impact of quantum effects, ...