Challenges to Ultralow-Power Semiconductor Device Operation

Francis Balestra

IMEP-LAHC, Minatec, Grenoble-Alpes University, 38016 Grenoble Cedex 1, France

1 Introduction

The historic trend in micro-/nanoelectronics over the last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition, and to develop many novel functionalities for future electronic systems. We are facing today dramatic challenges for “more Moore” and “more than Moore” applications: substantial increase of energy consumption and heating that can jeopardize future IC integration and performance, reduced performance due to limitation in traditional high-conductivity metal/low-κ dielectric interconnects, limit of optical lithography, heterogeneous integration of new functionalities for future nanosystems, and so on.

Therefore, many breakthroughs, disruptive technologies, novel materials, and innovative devices are needed in the next two decades.

With respect to the substantial reduction of the static and dynamic power of future high-performance/ultralow-power terascale integration logic and autonomous nanosystems, new materials and novel device architectures are mandatory for ultimate complementary metal-oxide-semiconductor (CMOS) and beyond-CMOS eras, as well as new circuit design techniques, architectures, and embedded software.

Alternative memories, especially PCRAM, RRAM, or MRAM will be useful for pushing ...

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