N. Ledentsov Jr, V. A. Shchukin, N. N. Ledentsov, J.-R. Kropp, S. Burger and F. Schmidt
VI Systems GmbH, Hardenbergstraße 7, Berlin, 10623, Germany
Zuse Institute Berlin (ZIB), Takustraße 7, Berlin, 14195, Germany and JCMwave GmbH, Bolivarallee 22, Berlin 14050, Germany
As silicon downscaling continues, the pitch size is gradually decreasing. The number of transistors per chip, consequently, further increases. Presently, the major IC manufacturers are planning to market 10 nm technology in 2015 with a further upgrade to 7 nm anticipated in 2017.1 2
With the growing number of transistors per chip and upgrades in the architecture, processor productivity continues to approximately double every year, increasing demands on the processor communication bandwidth. Consequently, the speed of the input/output (I/O) ports must also increase. Until recently, Moore's Law for data communications predicted that a fourfold increase in the I/O speed would be needed every 4–5 years. Thus far, this trend has been generally maintained in major communication standards. According to the IEEE Ethernet Roadmap, the single I/O bitrate should approach 100 Gb/s by 2017. Indeed the presently active IEEE 400G Ethernet Task Force for the related standard recently agreed on serial single channel bit data rate of 400 Gb/s in short distance communications.3 The aggregated transmission rate is to reach only ...