Handbook of 3D Integration, Volume 4

Chapter 83D Stacked DRAM Memories

Christian Weis Matthias Jung and Norbert Wehn

TU Kaiserslautern, Department of Electrical and Computer Engineering, Microelectronic Systems Design Research Group, Erwin‐Schroedinger‐Strasse 12, 67663, Kaiserslautern, Germany

While the computing performance of today's multiprocessor systems (MPSoCs) is ever increasing, the bandwidth (BW) delivered by the attached dynamic random‐access memory (DRAM) subsystem is limited. Here, 3D stacked DRAMs offer a very attractive alternative to complex high‐speed links and interconnects, as they increase largely the energy efficiency (EE) using (through‐silicon via) TSV technology. However, it is not sufficient to replace only the serial links by WideIO interfaces. Both the ...