Chapter 9Cost Modeling for 2.5D and 3D Stacked ICs
Mottaqiallah Taouil1, Said Hamdioui1, and Erik Jan Marinissen2
1 Delft University of Technology, EEMCS, Computer Engineering, Mekelweg 4, 2628CD Delft, The Netherlands
2 IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium
9.1 Introduction
Selecting appropriate and efficient test flows for 2.5D/3D stacked integrated circuits (2.5D/3D‐SICs) is crucial for overall cost optimization. In addition, different stacked die products may require different test flows executed after manufacturing; these flows may require different design‐for‐testability (DFT) features, which need to be incorporated in the various dies during their early design stages. Therefore, an appropriate cost model to ...
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