Handbook of 3D Integration, Volume 4

10Interconnect Testing for 2.5D‐ and 3D‐SICs

Shi‐Yu Huang

National Tsing Hua University, Department of Electrical Engineering, 101, Sec. 2, Kuang‐Fu Road, HsinChu, 30013, Taiwan

10.1 Introduction

In today's 3D‐IC technology, several functional dies can be integrated using various mechanisms, ranging from through‐silicon via (TSV)‐based die stacking, side‐by‐side placement on a silicon interposer, to redistribution layer (RDL) fabricated during wafer‐level post‐processing, as shown in Figure 10.1. In general, TSVs or interconnecting wires (either in an interposer or RDL) are regarded as pseudo IO's. They are bonded by micro‐bumps at the silicon interfaces when the multi‐die integrated circuit (IC) containing them is manufactured.

Figure 10.1 ...