15Test and Debug Strategy for TSMC CoWoS® Stacking Process‐Based Heterogeneous 3D‐IC: A Silicon Study
Sandeep K. Goel1, Saman Adham1, Min‐Jer Wang1, Frank Lee1, Vivek Chickermane2, Brion Keller2, Thomas Valind2, and Erik Jan Marinissen3
1Taiwan Semiconductor Manufacturing Company Ltd., Design Technology Platform (DTP), 2585 Junction Ave, San Jose, CA, 95134, USA
2Cadence Design Systems, 21 Oak Hill Avenue, Endicott, NY, 13760, USA
3IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Recent advances in semiconductor process technology, especially interconnects using through‐silicon vias (TSVs), enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the ...
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