Hands-On Embedded Programming with C++17

The VHDL code

In this section, we will take a look at the top-level entity in the VHDL project, to get an idea of what it does. This starts with the standard library includes for VHDL as shown:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.std_logic_unsigned.ALL; 
use IEEE.numeric_std.all; 
 
entity FleaFPGA_Ohm_A5 is   
   port( 
   sys_clock         : in        std_logic;  -- 25MHz clock input from external xtal oscillator. 
   sys_reset         : in        std_logic;  -- master reset input from reset header. 

This maps to the underlying FPGA's system clock and reset line. We can also see the way that port mapping works, defining the direction of the entity port and the type. Here, the type is std_logic, which is a standard logic signal of either a binary one or zero:

 n_led1 : buffer ...