book

Hardware Security

Name: Hardware Security
ISBN: 9780128124789

by Swarup Bhunia, Mark M. Tehranipoor

October 2018

Intermediate to advanced

526 pages

21h 23m

English

Morgan Kaufmann

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Cover image
Title page
Table of Contents
Copyright
Dedication
Preface
Acknowledgments
Chapter 1: Introduction to Hardware Security
Abstract1.1. Overview of a Computing System1.2. Layers of a Computing System1.3. What Is Hardware Security?1.4. Hardware Security vs. Hardware Trust1.5. Attacks, Vulnerabilities, and Countermeasures1.6. Conflict Between Security and Test/Debug1.7. Evolution of Hardware Security: A Brief Historical Perspective1.8. Bird's Eye View1.9. Hands-on Approach1.10. ExercisesReferences
Part 1: Background on Electronic Hardware
Chapter 2: A Quick Overview of Electronic Hardware
Abstract2.1. Introduction2.2. Nanoscale Technologies2.3. Digital Logic2.4. Circuit Theory2.5. ASICs and FPGAs2.6. Printed Circuit Board2.7. Embedded Systems2.8. Hardware-Firmware-Software Interaction2.9. ExercisesReferences

Chapter 3: System on Chip (SoC) Design and Test
Abstract3.1. Introduction3.2. The IP-Based SoC Life-Cycle3.3. SoC Design Flow3.4. SoC Verification Flow3.5. SoC Test Flow3.6. Design-for-Debug3.7. Structured DFT Techniques Overview3.8. At-Speed Delay Test3.9. ExercisesReferences
Chapter 4: Printed Circuit Board (PCB): Design and Test
Abstract4.1. Introduction4.2. Evolution of PCB and Components4.3. PCB Life Cycle4.4. PCB Assembly Process4.5. PCB Design Verification4.6. Hands-on Experiment: Reverse Engineering Attacks4.7. ExercisesReferences
Part 2: Hardware Attacks: Analysis, Examples, and Threat Models
Chapter 5: Hardware Trojans
Abstract5.1. Introduction5.2. SoC Design Flow5.3. Hardware Trojans5.4. Hardware Trojans in FPGA Designs5.5. Hardware Trojans Taxonomy5.6. Trust Benchmarks5.7. Countermeasures Against Hardware Trojans5.8. Hands-on Experiment: Hardware Trojan Attacks5.9. ExercisesReferences
Chapter 6: Electronics Supply Chain
Abstract6.1. Introduction6.2. Modern Electronic Supply Chain6.3. Electronic Components Supply Chain Issues6.4. Security Concerns6.5. Trust Issues6.6. Potential Countermeasures6.7. ExercisesReferences
Chapter 7: Hardware IP Piracy and Reverse Engineering
Abstract7.1. Introduction7.2. Hardware Intellectual Property (IP)7.3. Security Issues in IP-Based SoC Design7.4. Security Issues in FPGA7.5. Hands-on Experiment: Reverse Engineering and Tampering7.6. ExercisesReferences
Chapter 8: Side-Channel Attacks
Abstract8.1. Introduction8.2. Background on Side-Channel Attacks8.3. Power Analysis Attacks8.4. Electromagnetic (EM) Side-Channel Attacks8.5. Fault Injection Attacks8.6. Timing Attacks8.7. Covert Channels8.8. Hands-on Experiment: Side-Channel Attack8.9. ExercisesReferences
Chapter 9: Test-Oriented Attacks
Abstract9.1. Introduction9.2. Scan-Based Attacks9.3. JTAG-Based Attacks9.4. Hands-on Experiment: JTAG Attack9.5. ExercisesReferences
Chapter 10: Physical Attacks and Countermeasures
Abstract10.1. Introduction10.2. Reverse Engineering10.3. Probing Attack10.4. Invasive Fault Injection Attack10.5. ExercisesReferences
Chapter 11: Attacks on PCB: Security Challenges and Vulnerabilities
Abstract11.1. Introduction11.2. PCB Security Challenges: Attacks on PCB11.3. Attack Models11.4. Hands-on Experiment: Bus Snooping Attack11.5. ExercisesReferences
Part 3: Countermeasures Against Hardware Attacks
Chapter 12: Hardware Security Primitives
Abstract12.1. Introduction12.2. Preliminaries12.3. Physical Unclonable Function12.4. True Random Number Generator12.5. Design for Anti-Counterfeit12.6. Existing Challenges and Attacks12.7. Primitive Designs With Emerging Nanodevices12.8. Hands-on Experiment: Hardware Security Primitives (PUFs and TRNGs)12.9. ExercisesReferences
Chapter 13: Security and Trust Assessment, and Design for Security
Abstract13.1. Introduction13.2. Security Assets and Attack Models13.3. Pre-silicon Security and Trust Assessment for SoCs13.4. Post-silicon Security and Trust Assessment for ICs13.5. Design for Security13.6. ExercisesReferences
Chapter 14: Hardware Obfuscation
Abstract14.1. Introduction14.2. Overview of Obfuscation Techniques14.3. Hardware Obfuscation Methods14.4. Emerging Obfuscation Approaches14.5. Use of Obfuscation Against Trojan Attacks14.6. Hands-on Experiment: Hardware IP Obfuscation14.7. ExercisesReferences
Chapter 15: PCB Authentication and Integrity Validation
Abstract15.1. PCB Authentication15.2. Sources of PCB Signature15.3. Signature Procurement and Authentication Methods15.4. Signature Assessment Metric15.5. Emerging Solutions15.6. PCB Integrity Validation15.7. Hands-on Experiment: PCB Tampering Attacks (Modchip)15.8. ExercisesReferences
Part 4: Emerging Trends in Hardware Attacks and Protections
Chapter 16: System Level Attacks & Countermeasures
Abstract16.1. Introduction16.2. Background on SoC Design16.3. SoC Security Requirements16.4. Security Policy Enforcement16.5. Secure SoC Design Process16.6. Threat Modeling16.7. Hands-on Experiment: SoC Security Policy16.8. ExercisesReferences
Appendix A: The Hardware Hacking (HaHa) Platform for Hands-on Training
A.1. HaHa BoardA.2. Operation InstructionsA.3. Examples for Programming the FPGA and the MicrocontrollerA.4. Design Specifications
Index

Content preview from Hardware Security

Chapter 9

Test-Oriented Attacks

Abstract

Scan-based test is commonly used to increase testability and fault coverage. IEEE Standard 1149.1 defines test logic included in a design to test the interconnections between chips, and observe and control on-chip logic. However, these features have been exploited by the attackers to steal critical information, pirate intellectual property (IP) design, or illegally take control of the chip. Over the past decade, researchers in industry and academia have extensively studied, and developed, defenses to address the potential threats. This chapter first introduces the relationship between testability and security, then discusses the scan-based and JTAG attacks, and defenses for these threats, respectively. ...

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ISBN: 9780128124789

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Hardware Security

by Swarup Bhunia, Mark M. Tehranipoor

Test-Oriented Attacks

Abstract

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