Test-Oriented Attacks
Abstract
Scan-based test is commonly used to increase testability and fault coverage. IEEE Standard 1149.1 defines test logic included in a design to test the interconnections between chips, and observe and control on-chip logic. However, these features have been exploited by the attackers to steal critical information, pirate intellectual property (IP) design, or illegally take control of the chip. Over the past decade, researchers in industry and academia have extensively studied, and developed, defenses to address the potential threats. This chapter first introduces the relationship between testability and security, then discusses the scan-based and JTAG attacks, and defenses for these threats, respectively. ...
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