Parallel Evaluation of Fault Tree Expressions
Jefferson Amstutz SURVICE Engineering, USA
Abstract
Intel Xeon Phi coprocessors present a large amount of available parallelism in a single device. Large core counts (> 50) and wide SIMD vector instructions present a lot of available computation lanes of parallelism. Multithreaded applications became much more common when multicore processors became ubiquitous. Thread level parallelism has been made very easy with threading APIs such as OpenMP, CILK Plus, and Threading Building Blocks. In many cases, however, effective SIMD utilization is not as straightforward as multithreading. A purely scalar code can only use about 1/16th of the single precision FLOPs of a coprocessor, even while ...
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