Chapter 14. Supply Noise and Jitter Characterization

Hai Lan and Ralf Schmitt

Today’s high-speed I/O interfaces, operating at multi-gigabit per second data rates, present unprecedented design challenges [1]. Of all these challenges, achieving very low jitter, in order to meet increasingly tighter timing budgets, is one of the most difficult tasks. Timing jitter can be attributed to several different error sources. The most significant source of timing jitter is power supply noise. Power-integrity engineering has invested considerable effort to provide a stable power distribution network (PDN) that minimizes power noise. However, designing a PDN that makes power noise negligible in a high-speed interface is almost impossible, because the package ...

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