High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting

Chapter 15. Substrate Noise Induced Jitter

Hai Lan

It has been widely acknowledged that the substrate coupling noise is one of the bottleneck issues preventing the smooth and successful integration of the sensitive analog and RF circuits, with the noisy digital blocks, in a System-on-Chip (SOC) [1]. When sensitive circuits are integrated with noisy digital circuits sharing a common substrate, substrate noise is inevitable, primarily due to the switching activity of the digital circuits. The injected noise propagates through the entire substrate. This noise attenuates differently, depending on the substrate type, doping profile, backside epoxy choice, and layout implementation, but it eventually arrives at the sensitive circuit blocks. In a 3-D ...