Chapter 17. Signal Conditioning

Jihong Ren and Jared Zerbe

During the past decade, computing platforms have evolved from single-core processors to multi-core processors. Currently, eight-core processors are available in the consumer market. It seems certain the world is entering into a multi-core era. However, without adequate off-chip bandwidth, I/O speed will be the factor limiting system performance. A 256-core processor, assuming four-way SIMD FMACs at 2.5GHz–5GHz, would need terabytes/s of off-chip I/O bandwidth. Package technology has simply not kept pace with the rapid growth in required bandwidth. In 2007, the maximum pin-count for high-performance chips was about 2100; it is expected to grow to only about 5400 pins by 2017 [1]. Consequently, ...

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