Figure 1-1 shows a typical PA-RISC processor. The architecture provides for a translation lookaside buffer (TLB), which is used to assist in translating virtual addresses to physical addresses. The inclusion of a cache is optional, but most PA-RISC processors do have at least some amount of cache. The architecture also provides for assist processors such as a floating-point processor to assist in complex operations.
Figure 1-1. Processor Block Diagram
Central Processing Unit
The CPU itself contains the system's register set, control logic, and execution logic. The register set, discussed in detail below, is where all of the computation ...