The PA-RISC architecture provides for several sets of registers. Of particular interest to us are the general registers, space registers, and some of the control registers.

General Registers

PA-RISC has 32 general purpose registers. In PA-RISC 2.0, these are 64-bit registers; prior to PA-RISC 2.0, these registers are 32 bits wide. The architecture itself defines specific uses for only a few of these registers:

  • GR0— Permanent zero. Reads from this register always return a zero. Writes to this register are discarded.

  • GR1— Target of ADDIL. When the ADD IMMEDIATE LONG (ADDIL) instruction is executed, the result is always placed in GR1. This register can also be used for other purposes.

  • GR2— Target of B,L. This register is used as the target ...

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