HyperTransport™ System Architecture

Book description

HyperTransport™ (HT) technology promises to revolutionize connectivity for computers, servers, embedded systems, and networking and tele-communications equipment. It is a high-speed, low latency, point-to-point, packetized link that enables chips to transfer data at peak rates of up to 12.8 Gigabytes per second, far greater than existing bus technologies. Furthermore, HyperTransport improves reliability and reduces board design complexity. It is scalable and compatible with legacy PC buses, SNA, and PCI.

HyperTransport™ System Architecture provides a comprehensive, technical guide to HyperTransport technology. It opens with an overview of HT systems, highlighting the technology's fundamental principles, basic architecture, and its many advantages. The book goes on to detail all facets of HyperTransport systems, including the protocol, I/O, routing, configuration, and more. It also features important performance considerations and addresses critical compatibility issues.

Essential topics covered include:

  • Signal groups

  • Packet protocol, covering control and data packets

  • HT flow control, and how it differs from PCI flow control

  • I/O ordering rules, including upstream, downstream, and host ordering requirements

  • Interrupts, error detection, and error handling

  • HT system management

  • Routing packets, covering point-to-point topology and HT's fairness algorithm

  • Device configuration

  • The electrical environment, including power requirements and signaling characteristics

  • HyperTransport bridges

  • Double-hosted chains

  • Anticipated networking extensions

  • PCI, PCI-X, AGP, and X86 compatibility issues

A chapter is dedicated to transaction examples illustrating the practical application of HyperTransport technology.

A MindShare PC System Architecture Series book, HyperTransport™ System Architecture provides complete, authoritative, and detailed information necessary for developers, networking professionals, and anyone interested in implementing and deploying HT systems.

MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. Each title explains the architecture, features, and operations of systems built using one particular type of chip or hardware specification.


Table of contents

  1. Copyright
  2. PC System Architecture Series
  3. Figures
  4. Tables
  5. Acknowledgments
  6. About This Book
  7. Overview of HyperTransport
    1. Introduction to HyperTransport
      1. Background: I/O Subsystem Bottlenecks
      2. What HT Brings
    2. HT Architectural Overview
      1. General
      2. Transfer Types Supported
      3. HT Signals
      4. Scalable Performance
      5. Extending the Topology
      6. Packetized Transfers
      7. HyperTransport Protocol Concepts
      8. Managing the Links
  8. HyperTransport Core Topics
    1. Signal Groups
      1. Introduction
      2. The Signal Groups
      3. The High Speed Signals (One Set In Each Direction)
      4. Scaling Hazards: Burden Is On The Transmitter
      5. The Low Speed Signals
      6. Where Are The Interrupt, Error, And Wait State Signals?
      7. No Arbitration Signals Either
    2. Packet Protocol
      1. The Packet-Based Protocol
      2. The Two Packet Types: Control And Data
      3. The Need To Interleave Control And Data Packets
      4. Packet Format: Control Packets
    3. Flow Control
      1. The Problem
      2. HyperTransport Flow Control: Overview
      3. Flow Control, A System View
      4. Flow Control Buffer Arrangement
      5. Example: Initialization And Use Of The Counters
      6. A Few Implementation Notes
    4. I/O Ordering
      1. The Purpose Of Ordering Rules
      2. Introduction: Three Types Of Traffic Flow
      3. The Ordering Rules
    5. Transaction Examples
      1. Packets As Transaction Building Blocks
      2. Transaction Examples: Introduction
      3. Example 1: NOP Information Packet
      4. Generic Request And Response Packet Formats
      5. Example 2: Non-Posted WrSized (Dword) Transaction
      6. Example 3: Posted Byte Write Request
      7. Example 4:Dword Read Request
      8. Example 5:Byte Read Request
      9. Example 6:Flush Request
      10. Example 7:Fence Request
      11. Example 8:Atomic Read-Modify-Write
      12. Example 9: WrSized Request Crosses A Bridge
    6. HT Interrupts
      1. Introduction
      2. Discovering a Device's Interrupt Requirements
      3. The Interrupt Message Address Range
      4. Interrupt Requests
      5. Interrupt Discovery and Configuration Capability Block
    7. System Management
      1. System Management Transactions
      2. HT Link Disconnect/Reconnect Sequence
      3. Example SM Sequence: Link Initialization Disconnect
    8. Error Detection And Handling
      1. Introduction
      2. The Error Types
      3. Error Reporting
    9. Routing Packets
      1. Packet Routing: Shared Bus vs. Point-Point Topology
      2. Review Of Packet Types And Formats
      3. Directed vs. Broadcast Requests
      4. Accepting Packets
      5. Forwarding Packets
      6. Rejecting Packets
      7. Host Bridge Behavior
      8. HyperTransport Bridges: Additional Routing Rules
      9. Tunnel Fairness And Forward Progress
    10. Reset & Initialization
      1. General
      2. Cold Reset
      3. Link Initialization
      4. Warm Reset
      5. LDTSTOP# Disconnect Sequence
    11. Device Configuration
      1. HyperTransport Uses PCI Configuration
      2. What PCI Configuration Accomplishes
      3. HyperTransport System Limits
      4. Configuration Accesses: Reaching All Devices
      5. Review: How PCI Handles Configuration Accesses
      6. How HyperTransport Handles Configuration Accesses
      7. HyperTransport Configuration Space Format
    12. Electrical
      1. Background and Introduction
      2. Power Requirements
      3. Differential Signaling Characteristics
      4. Single-Ended Signaling Characteristics
      5. Differential Timing Characteristics
      6. Testing
    13. Clocking
      1. Introduction
      2. Clock Initialization
      3. Synchronous Clock Mode
  9. HyperTransport Optional Topics
    1. HyperTransport Bridges
      1. HyperTransport Bridges Uses PCI Configuration
      2. Basic Jobs Of A HyperTransport Bridge
      3. How Does The Bridge Manage It All?
    2. Double-Hosted Chains
      1. Introduction
      2. Two Types Of Double-Hosted Chains
    3. HT Power Management
      1. Background
      2. Reporting Power Management Events to the Host Bridge
      3. Reporting Host Power Management Events to SMC
      4. Reporting Power Management Events to HT Devices
      5. Signaling Wakeup
      6. X86 Power Management Support
    4. Networking Extensions Overview
      1. An Important Note
      2. Server And Desktop Topologies Are Host-Centric
      3. Some Systems Are Not Host-Centric
      4. The Need For Networking Extensions
      5. Summary Of Anticipated Networking Extension Features
  10. HyperTransport Legacy Support
    1. I/O Compatibility
      1. Introduction
      2. PCI Bus Issues
      3. PCI-X Bus Issues
      4. AGP Bus Issues
      5. ISA/LPC Buses
    2. Address Remapping
      1. Introduction
      2. The Address Remapping Capability Block
      3. I/O Address ReMapping
      4. DownStream HT to Expansion Bus Memory Mapping
      5. DMA Mapping
    3. X86 CPU Compatibility
      1. Background
      2. X86 Interrupt Support
      3. The A20 Mask
      4. System Management Mode (SMI# & SMIACT#)
      5. Numeric Error Handling (FERR# and IGNNE#)
      6. X86 Instructions and Special Cycles
  11. Glossary of Terms
  12. Index

Product information

  • Title: HyperTransport™ System Architecture
  • Author(s): MindShare, Inc., Don Anderson, Jay Trodden
  • Release date: February 2003
  • Publisher(s): Addison-Wesley Professional
  • ISBN: 0321168453